ucc1810 UCC2810 ucc3810 02/99 features single oscillator synchronizes two pwms 150 a startup supply current 2ma operating supply current operation to 1mhz internal soft start full-cycle fault restart internal leading edge blanking of the current sense signal 1 amp totem pole outputs 75ns typical response from current sense to output 1.5% tolerance voltage reference description the ucc3810 is a high-speed bicmos integrated circuit which imple- ments two synchronized pulse width modulators for use in off-line and dc-to-dc power supplies. the ucc3810 provides perfect synchronization between two pwms by us- ing the same oscillator. the oscillators sawtooth waveform can be used for slope compensation if required. using a toggle flip flop to alternate between modulators, the ucc3810 en- sures that one pwm will not slave, interfere, or otherwise affect the other pwm. this toggle flip flop also ensures that each pwm will be limited to 50% maximum duty cycle, insuring adequate off-time to reset magnetic el- ements. this ic contains many of the same elements of the uc3842 current mode controller family, combined with the enhancements of the ucc3802. this minimizes power supply parts count. enhancements include leading edge blanking of the current sense signals, full cycle fault restart, cmos output drivers, and outputs which remain low even when the supply voltage is re- moved. dual channel synchronized current mode pwm block diagram udg-92062-1
2 ucc1810 UCC2810 ucc3810 absolute maximum ratings v cc voltage (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v v cc current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma out1, out2 current, peak, 5% duty cycle. . . . . . . . . . . . 1a out1, out2 energy (capacitive load) . . . . . . . . . . . . . . 20 m j analog inputs (fb1, fb2, cs1, cs2, sync). . . . C0.3v to 6.3v operating junction temperature . . . . . . . . . . . . . . . . . . +150 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 seconds) . . . . . . . . . . 300 c note 1 : all voltages are with respect to gnd. all currents are positive into the specified terminals. note 2 : consult unitrode integrated circuits product & appli- cations handbook for information regarding thermal specifications and limitations of packages. note 3: in normal operation, v cc is powered through a current limiting resistor. absolute maximum of 11v applies when driven from a low impedance such that the v cc current does not exceed 20ma. connection diagram electrical characteristics: unless otherwise stated, these specifications apply for C55 c t a 125 c for ucc1810; C40 c t a 85 c for UCC2810; 0c t a 70c for ucc3810; v cc = 10v (note 4); r t = 150k; c t = 120pf; no load; t a = t j . all parameters are the same for both channels. parameter test conditions min typ max units reference section output voltage t j = 25 c 4.925 5.000 5.075 v load regulation 0ma < i ref < 5ma 5 25 mv line regulation uvlo stop threshold voltage +0.5v < v cc < shunt voltage 12 mv output voltage full temperature range, 0ma < i ref < 5ma 4.85 5.00 5.10 v output noise voltage 10hz < f < 10khz, t j = +25 c (note 10) 235 m v long term stability t a = +125 c, 1000 hours (note 10) 5 mv output short circuit current C8 C25 ma oscillator section oscillator frequency r t = 30k, c t = 120pf (note 5) 840 940 1040 khz oscillator frequency r t = 150k, c t = 120pf (note 5) 200 220 240 khz temperature stability (note 10) 2.5 % peak voltage 2.5 v valley voltage 0.05 v peak-to-peak amplitude 2.25 2.45 2.65 v sync threshold 0.80 1.65 2.2 v sync input current sync = 5v 30 m a error amplifier section fb input voltage comp = 2.5v 2.44 2.50 2.56 v fb input bias current 1 m a open loop voltage gain 60 73 db unity gain bandwidth (note 10) 2 mhz comp sink current fb = 2.7v, comp = 1v 0.3 1.4 3.5 ma comp source current fb = 1.8v, comp = 4v C0.2 C0.5 C0.8 ma minimum duty cycle comp = 0v 0 % comp soft start rise time fb = 1.8v, rise from 0.5v to refC1.5v 5 ms dil-16, soic-16 (top view) j or n package, dw package
3 ucc1810 UCC2810 ucc3810 electrical characteristics: unless otherwise stated, these specifications apply for C55 c t a 125 c for ucc1810; C40 c t a 85 c for UCC2810; 0c t a 70c for ucc3810; v cc = 10v (note 4); r t = 150k; c t = 120pf; no load; t a = t j . all parameters are the same for both channels. parameter test conditions min typ max units current sense section gain (note 6) 1.20 1.55 1.80 v/v maximum input signal comp = 5v (note 7) 0.9 1.0 1.1 v cs input bias current 200 na cs to out propagation delay cs steps from 0v to 1.2v, comp = 2.5v 75 ns cs blank time (note 8) 55 ns cs overcurrent threshold 1.35 1.55 1.85 v comp to cs offset cs = 0v 0.65 0.95 1.4 v pwm section maximum duty cycle r t = 150k, c t = 120pf (note 10) 45 49 50 % maximum duty cycle r t = 30k, c t = 120pf (note 10) 40 45 48 % minimum on time cs =1.2v, comp = 5v 130 ns output section out low level i out = 20ma 0.12 0.42 v i out = 200ma 0.48 1.10 v i out = 20ma, v cc = 0v 0.7 1.20 v out high level (v cc - out) i out = C20ma 0.15 0.42 v i out = C200ma 1.20 2.30 v out rise time c out = 1nf 20 50 ns out fall time c out = 1nf 30 60 ns undervoltage lockout section start threshold 9.9 11.3 13.2 v stop threshold 7.5 8.3 9.5 v start to stop hysteresis 1.7 3.0 4.7 v enable2 input bias current enable2 = 0v C20 C35 C55 m a enable2 input threshold voltage 0.80 1.53 2.00 v overall section startup current v cc < start threshold voltage 0.15 0.25 ma operating supply current, outputs off v cc = 10v, fb = 2.75v 2.0 3.0 ma operating supply current, outputs on v cc = 10v, fb = 0v, cs = 0v, r t = 150k 3.2 5.1 ma operating supply current, outputs on v cc = 10v, fb = 0v, cs = 0v, r t = 30k 8.5 14.5 ma v cc internal zener voltage i cc = 10ma (note 9) 11.0 12.9 14.0 v v cc internal zener voltage minus start threshold voltage 0.4 1.2 v note 4: adjust v cc above the start threshold before setting at 10v. note 5: oscillator frequency is twice the output frequency. f rt ct osc ? 4 note 6: current sense gain a is defined by: a vcomp vcs vcs v = d d 008 . . note 7: parameter measured at trip point of latch with fb = 0v. note 8: cs blank time is measured as the difference between the minimum non-zero on-time and the cs to out delay. note 9: start threshold voltage and v cc internal zener voltage track each other. note 10: guaranteed by design. not 100% tested in production.
4 ucc1810 UCC2810 ucc3810 pin descriptions comp1, comp2 : the low impedance outputs of the er- ror amplifiers. cs1, cs2 : the current sense inputs to the pwm com- parators. these inputs have leading edge blanking. for most applications, no input filtering is required. leading edge blanking disconnects the cs inputs from all inter- nal circuits for the first 55ns of each pwm cycle. when used with very slow diodes or in other applications where the current sense signal is unusually noisy, a small current sense rc filter may be required. ct : the timing capacitor of the oscillator. recom- mended values of c t are between 100pf and 1nf. con- nect the timing capacitor directly across c t and gnd. enable2 : a logic input which disables pwm 2 when low. this input has no effect on pwm 1. this input is in- ternally pulled high. in most applications it can be left floating. in unusually noisy applications, the input should be bypassed with a 1nf ceramic capacitor. this input has ttl compatible thresholds. fb1, fb2 : the high impedance inverting inputs of the error amplifiers. gnd : to separate noise from the critical control circuits, this part has two different ground connections: gnd and pwrgnd. gnd and pwrgnd must be electrically connected together. however, use care to avoid cou- pling noise into gnd. out1, out2 : the high current push-pull outputs of the pwm are intended to drive power mosfet gates through a small resistor. this resistor acts as both a cur- rent limiting resistor and as a damping impedance to minimize ringing and overshoot. pwrgnd : to separate noise from the critical control circuits, this part has two different ground connections: gnd and pwrgnd. gnd and pwrgnd must be elec- trically connected together. ref : the output of the 5v reference. bypass ref to gnd with a ceramic capacitor 3 0.01 m f for best perfor- mance. rt : the oscillator charging current is set by the value of the resistor connected from r t to gnd. this pin is regu- lated to 1v, but the actual charging current is 10v/r t . recommended values of r t are between 10k and 470k. for a given frequency, higher timing resistors give higher maximum duty cycle and slightly lower overall power consumption. supply current decreases with in- creased r t by the relationship: d icc v rt = 11 for more information, see the detailed oscillator block diagram. sync : this logic input can be used to synchronize the oscillator to a free running oscillator in another part. this pin is edge triggered with ttl thresholds, and requires at least a 10ns wide pulse. if unused, this pin can be grounded, open circuited, or connected to ref. vcc : the power input to the ic. this pin supplies cur- rent to all functions including the high current output stages and the precision reference. therefore, it is criti- cal that v cc be directly bypassed to pwrgnd with an 0.1 m f ceramic capacitor. leading edge blanking and current sense figure 1. shows how an external power stage is con- nected to the ucc3810. the gate of an external power n-channel mosfet is connected to out through a small current limiting resistor. for most applications, a 10 w resistor is adequate to limit peak current and also practical at damping resonances between the gate driver and the mosfet input reactance. long gate lead length increases gate capacitance and mandates a higher se- ries gate resistor to damp the rlc tank formed by the lead, the mosfet input reactance, and the ucc3810 driver output resistance. the ucc3810 features internal leading edge blanking of the current sense signal on both current sense inputs. the blank time starts when out rises and continues for 55ns. during that 55ns period, the signal on cs is ig- nored. for most pwm applications, this means that the cs input can be connected to the current sense resistor as shown above. however, high speed grounding prac- tices and short lead lengths are still required for good performance. application information
5 ucc1810 UCC2810 ucc3810 figure 1. detailed block diagram. application information (cont.) oscillator the ucc3810 oscillator generates a sawtooth wave at ct. the sawtooth rise time is set by the resistor from rt to gnd. since rt is biased at 1v, the current in rt is 1v/rt. the actual charging current is 10 times higher. the fall time is set by an internal transistor on-resistance of approximately 100 w . during the fall time, all outputs are off and the maximum duty cycle is reduced below 50%. larger timing capacitors increase the discharge time and reduce frequency. however, the percentage maximum duty cycle is only a function of the timing resis- tor rt and the internal 100 w discharge resistance. error amp output stage the ucc3810 error amplifiers are operational amplifiers with low output resistance and high input resistance. the output stage of one error amplifier is shown above. this output stage allows the error amplifier output to swing close to gnd and as high as one diode drop below 5v with little loss in amplifier performance. figure 2. oscillator. figure 3. error amp output stage.
6 ucc1810 UCC2810 ucc3810 figure 9. maximum duty cycle vs. frequency. figure 5. oscillator frequency vs. temperature. figure 7. oscillator frequency vs. r t and c t. figure 8. maximum duty cycle vs r t . figure 4. error amp and gain phase response. typical characteristics figure 6. i cc vs. oscillator frequency.
7 ucc1810 UCC2810 ucc3810 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 application information (cont.) figure 10. typical application. udg-94022
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
|
